1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a capacitor in a highly integrated DRAM cell.
2. Background of the Related Art
As semiconductor memories are developed from mega class to giga class, the cell size reduces and the semiconductor fabrication process gets very complicated. A related art method for fabricating a capacitor in a giga class DRAM cell will be explained in detail with reference to the attached drawings. FIGS. 1a.about.1d illustrate plan views of DRAM cells showing the steps of the related art process for fabricating a capacitor in the DRAM cell, and FIGS. 2a.about.2e illustrate section views across lines I-I' showing the steps of the related art process for fabricating a capacitor in the DRAM cell.
Referring to FIGS. 1a and 2a, an active region 2 and a field region (i.e., a region excluding a the active region 2) are first defined on a semiconductor substrate 1 and a field oxide film 3 is formed on the field region. A plurality of wordlines (i.e., gate electrodes) 4 and cap insulating films (not shown) are formed on the semiconductor substrate 1 perpendicular to the active region 2 at fixed intervals such that every action region 2 has two wordlines passing across the active region 2. The wordlines 4 are used as masks in injecting impurity ions into the active region 2 to form source/drain impurity regions (not show). Sidewall insulating films 5 are formed at both sides of the wordlines 4.
As shown in FIGS. 1b and 2b, polysilicon is deposited on an entire surface of the substrate, and then selectively removed by a chemical mechanical polishing process (CMP) to expose a surface of the cap insulating film on the wordline. The polysilicon layer is then subjected to patterning by photolithography, and a plurality of first plugs 6 and 6a are formed on the active region 2 between wordlines 4. As shown in FIG. 1b, the first plug 6a formed between two adjacent wordlines 4 in each active region is extended to portions at which a bitline is to be formed.
As shown in FIGS. 1c and 2c, a thick interlayer dielectric film (ILD) (e.g., a thick oxide film) 7 is formed on an entire surface, and then planarized. A contact hole 8 is then formed in a portion of the first plug 6a which is extended to the bitline. A tungsten layer and a cap insulting film are deposited on the entire surface of the substrate, subjected to patterning by photo etching to form a bitline 9 and a cap insulating film 10 in a direction perpendicular to the wordline. An insulating film is deposited on the entire surface, and etched back to form insulating sidewalls 11 at both sides of the bitline 9, and to expose surfaces of the first plugs 6 and 6a by making a slight over etching of the insulating film in the etch back of the insulating film such that the interlayer dielectric film 7 on the first plugs 6 and 6a is partially removed.
As shown in FIGS. 1d and 2d, polysilicon is deposited on an entire surface, removed by CMP to expose a surface of the cap insulating film 10 on the bitline 9. The polysilicon layer is then subjected to patterning by photolithography to leave the polysilicon only on the first plug 6, thus forming a second plug 12. Referring to FIG. 2e, a storage electrode 13 of a capacitor is formed on the second plug 12. A dielectric film 14 is formed on a surface of the capacitor storage electrode 13, and a plate electrode 15 is then formed on the dielectric film 14, thus completing a capacitor.
The related art method for fabricating a capacitor in a DRAM cell has the following problems. Because two plugs are formed, the related art method has many fabrication steps. In addition, the storage electrode of the capacitor has to be patterned by photolithography. This further complicates the fabrication process.